3di_log
March 9th, 2005, 04:19 AM
This topic is really in no relation to programming :)
But I really need your help.
I've read the first two chapters of this book, but confused by several representations in it. I'm not familiar with this area (that's why i read it) , so if you've read it, or you are experienced in this area, please give me some instructions.
Thx.
In A - 38 ( Appendix a - 38 ) , it introducesd two changes to reduce branch hazards in pipeline, and one is to write PC of the instruction in the IF phase.
Is this possible? Say, if it is a branch instruction, then the data to write into PC needs the output of ID phase ( If not, only increment the PC by 1, in my opinion) ?
And now branch instruction only needs 2 processor-cycles (IF-ID) , and store needs 4, and others register-register operations only needs 4 also? (the MEM stage is not required since the Saving of PC is moved to IF stage, then we could omit it or we still have to do a null-op in this stage, then these operations will still needs 5)
By the way, I'm still unsure why the architecture used as the example in the book is named as "MIPS", an abbreviation of "Million Instructions Per Second" ?
PC - Program counter
IF - Instruction Fetch
ID - Instruction Decode
MEM - Memory Access
WB - Write Back
But I really need your help.
I've read the first two chapters of this book, but confused by several representations in it. I'm not familiar with this area (that's why i read it) , so if you've read it, or you are experienced in this area, please give me some instructions.
Thx.
In A - 38 ( Appendix a - 38 ) , it introducesd two changes to reduce branch hazards in pipeline, and one is to write PC of the instruction in the IF phase.
Is this possible? Say, if it is a branch instruction, then the data to write into PC needs the output of ID phase ( If not, only increment the PC by 1, in my opinion) ?
And now branch instruction only needs 2 processor-cycles (IF-ID) , and store needs 4, and others register-register operations only needs 4 also? (the MEM stage is not required since the Saving of PC is moved to IF stage, then we could omit it or we still have to do a null-op in this stage, then these operations will still needs 5)
By the way, I'm still unsure why the architecture used as the example in the book is named as "MIPS", an abbreviation of "Million Instructions Per Second" ?
PC - Program counter
IF - Instruction Fetch
ID - Instruction Decode
MEM - Memory Access
WB - Write Back